The present invention relates to pipeline design for use in an asynchronous microprocessor. More specifically, the invention relates to a counterflow pipeline, i.e., a pipeline having oppositely flowing and interconnected instruction and result pipelines between which instruction and result data may be compared and exchanged.
The basic concept of a counterflow pipeline is introduced in commonly assigned, U.S. Pat. No. 5,572,690, the entire specification of which is incorporated herein by reference. According to that application, a two-phase or transition signaling protocol is used to facilitate movement of instruction and result packets in their respective pipelines.
In the design of an asynchronous circuit, the lack of a global clock necessitates the use of a communication protocol by which requests may be transmitted to the various circuit modules to begin execution of their functions and by which the circuit modules may acknowledge completion of their functions. Typically, two types of communication protocols are employed in asynchronous circuit design. The first is known as two-phase or transition signaling and involves the use of logic signal transitions (in either direction) to indicate the occurrence of an event such as a request or an acknowledge. The protocol is known as two-phase because the interaction between circuit modules is characterized by one of two states, i.e., either a request is outstanding or it is not. This design paradigm is advantageous in that it is aligned with the typical system designer's model of asynchronous system behavior in that transitions map well onto the discrete events which characterize asynchronous system behavior. For this reason, systems employing two-phase signaling tend to be easier to conceptualize and model than functionally similar systems using four-phase signaling.
Unfortunately, according to the two-phase protocol, to determine whether parity exists between a request line and an acknowledge line specialized logic gates such as Muller C elements and exclusive-OR gates are required. Such specialized gates are slower and more complex than "standard" AND and OR gates thus introducing undesirable delays and circuit overhead. Moreover, two-phase signaling often requires additional circuitry to represent the larger number of control states typically required with two-phase signaling.
By contrast, four-phase or level signaling employs specific levels on, for example, a request line and an acknowledge line to control circuit behavior. For example, if a first circuit module transmits data to a second circuit module, the first circuit module first transmits a request to the second circuit module by setting its request line high. When the second circuit module has latched the data its acknowledge line will go high, thereby notifying the first circuit module that the data has been successfully transferred. The request is then reset, thereby permitting the resetting of the acknowledge line soon thereafter. This protocol is referred to as four-phase because of the four different possible states of the request and acknowledge lines.
Although a complete cycle in the four-phase protocol requires four signal transitions rather than the two required by the two-phase protocol, the apparent inefficiency is mitigated because the state of the request and acknowledge lines can be detected using standard AND and OR gate implementations. Furthermore, the circuit redundancies which are often necessary for a two-phase protocol to provide distinct logic levels to operate data latches are eliminated. Thus, the apparent inefficiency of a four-phase protocol is counterbalanced by the efficiencies of a faster, simpler control circuit design.